1. Field of Invention
This invention relates generally to methods of programming, erasing and reading a memory structure, and more particularly to methods of programming, erasing and reading a flash memory.
2. Background
Electrically erasable programmable read-only-memories (EEPROMs) are widely used as memory components for personal computers and electronic equipment. A conventional EEPROM memory cell comprises a floating gate transistor structure that is programmable, erasable and can store data. However, the conventional EEPROM suffers from a slow storage and retrieval time of typically around 150 ns to 200 ns. Recently, a faster EEPROM, such as a flash memory, has been developed having a storage and retrieval time of about 70 ns to 80 ns.
A conventional floating gate transistor relies on hot electrons and the nature of Fowler-Nordheim tunneling to store data. For example, when the flash memory stores data, a high voltage, on the order of 8 volts, is applied between the source region and the drain region. A high voltage is also applied to the control gate. Hot electrons generated in the channel region will flow into the floating gate through the tunneling oxide layer near the drain region to be stored in the floating gate. By this mechanism, the threshold voltage of the floating gate transistor is raised to store data.
When the data is to be erased, a negative voltage is applied to the control gate. The electrons previously trapped in the floating gate will tunnel through the tunneling oxide layer to erase the data, and the floating gate comes back to the uncharged state. In the erasing process, the erasing time takes a long time to ensure the uncharged state of the floating gate.
FIG. 1 is a schematic layout of a conventional flash memory. FIGS. 2 to 4 are cross sectional views taken along the line I--I in FIG. 1, schematically illustrating the fabrication process. FIGS. 5 to 6 are cross sectional views taken along the line II--II in FIG. 1, schematically illustrating the fabrication process. The manufacturing method of the conventional flash memory is described as below.
Referring to the FIGS. 2 and 5, first, on a substrate 10, a pad oxide layer (not shown) is formed by thermal oxidation. Active regions are then defined by forming field oxide layer 14, using local oxidation. The pad oxide layer is then removed away by wet etching. Next, by thermal oxidation, a tunneling oxide layer 12 with a thickness of about 100 .ANG., is formed on the surface of the device regions. Then, a polysilicon layer is formed on the tunneling oxide layer 12 by low pressure chemical vapor deposition (LPCVD). The polysilicon layer is then defined by photolithography and etching to form a polysilicon layer 16 with a thickness of about 1500 .ANG..
Next, an inter-poly dielectric layer is formed by, for example, LPCVD, and covers the polysilicon layer 16. The inter-poly dielectric layer has a thickness of about 250 .ANG. and constructed by oxide/nitride/oxide layers. Then, another layer of polysilicon with a thickness of about 3000 .ANG. is formed on the polysilicon layer 16. Both the inter-poly dielectric layer and the polysilicon layer are patterned by photolithography and etching to be an inter-poly dielectric layer 18 and polysilicon layer 20. The polysilicon layer 20 is utilized as a control gate of the flash memory.
Then, by using the polysilicon layer 20 as a mask, the polysilicon layer 16 is further patterned by etching. A process of implanting ions is next performed by using the polysilicon layer 20 as a mask to form an implantation region 22 with a higher density of doped ions than that of the substrate. A gate electrode of the flash memory is constituted by the polysilicon layer 20, inter-poly dielectric layer 18, polysilicon layer 16 and tunneling oxide layer 12.
Thereafter, the semiconductor substrate is patterned by using a mask (not shown), exposing the implantation region 22 located at one side of the gate electrode. A process of implanting ions is next performed by using a tilted angle to implant dopant into substrate 10, and a process of annealing is performed to form a diffusion region 24. The diffusion region 24 is located at around of the implantation region 22, elongated to the place below the gate electrode. The implantation region 22 is surrounded by the diffusion region 24. The mask (not shown) is removed after the diffusion region 24 is formed.
Referring to FIG. 3, a layer of oxide is deposited over the whole surface of the substrate structure by using LPCVD. An etching back method is then performed on the oxide layer to form spacers 26 on sidewalls of the gate electrode. Thereafter, an implantation region 28 is formed by using a process of implanting ions to implant ions into the substrate 10 as illustrated in FIG. 3. The cross sectional view taken along with the line II--II in FIG. 3 is the same as the FIG. 5.
Referring to FIGS. 4 and 6, a dielectric layer 30 is formed over the whole substrate structure by using LPCVD. A contact opening 32 is formed on the dielectric layer 30, exposing the implantation region 22, by using lithography and etching. Then, a metal layer 34 acting as a bit line is formed over the dielectric layer 30 by LPCVD, filling the contact opening 32 so that the metal layer 34, also known as the bit line, is electrically coupled to the implantation region 22. A conventional procedure is followed to complete fabrication of the flash memory. This procedure is familiar to those skilled in the art and therefore is not described here.
FIG. 7 illustrates a partial circuit diagram of a conventional read only access memory. FIG. 7 is an example of a 2.times.3 matrix including 2 arrays or rows of memory cells and 3 columns of memory cells. FIG. 7 shows 6 memory cells, 2 word lines along the rows and 3 bit lines along the columns. Each memory cell in one array or rows is coupled to different bit lines BL but coupled to one equal word line WL. Memory cells in one column coupled to one equal bit line BL but memory cells in different arrays are coupled to different word lines WL.
Number 121, 122, 123, 124, 125, and 126, each represent one memory cell. Memory cells 121 and 124 both are coupled to the bit line BL1 and are coupled to the word line WL1 and the word line WL2, respectively. Memory cells 122 and 125 both are coupled to the bit line BL2 and are coupled to the word line WL1 and the word line WL2, respectively. Memory cells 123 and 126 both are coupled to the bit line BL3 and are coupled to the word line WL1 and the word line WL2, respectively. Memory cells 121, 122 and 123 are all coupled to the word line WL1 and memory cells 124, 125 and 126 are all coupled to the word line WL2. Another terminal of the memory cells is coupled to the ion implantation region Vss.
The conventional memory cells have several drawbacks. First, during programming and reading, different voltage has to be supplied to the corresponding bit line BL, word line WL and ion implantation region Vss of each memory cell, which is complex.
For example, during the programming of the memory cell 122, 12 volts has to be supplied to the word line WL1, 8 volts has to be supplied to the bit line BL2 and the ion implantation region Vss has to be grounded. However, during the programming of other memory cells in the same array, another voltage has to be supplied to the corresponding bit line BL of the memory cell. Therefore, the programming procedure is quite laborsome. Second, it is also complicated during the procedures of "read" or "erase". During the procedure of "read" or "erase", different voltage has to be supplied to the corresponding bit line BL, word line WL and ion implantation region Vss of each memory cell. Moreover, one procedure of erase can erase only one row of memory cells, because one Word line WL only couples to one row of memory cells. Therefore, the erasing procedure is quite laborsome.
In the conventional method described above, it is difficult to effectively reduce the flash memory size because it is limited by the size of the contact opening. The existence of the field oxide layer 14 also affects the size reduction and planarization of the active region. Besides that, since the metal layer 34 also has to fill the contact opening 32 in order to serve as the bit line, interference due to signal reflection from the metal layer 34 is inevitable.